Cellular telephony systems provide coverage across broad areas using cells, where each cell is serviced by a corresponding cellular base station. A conventional base station is located adjacent the bank of antennas and amplifiers the base station uses to service its cell. As cellular providers support increasingly sophisticated services such as 3G (the third generation of standards for mobile networking), the real estate demands for the base stations necessary to support each cell in a cellular network increase. It was conventional for a base station to be entirely vendor-specific such that the designs and protocols used in a base station would depend upon the particular manufacturer used to provide the base station. This lack of standardization leads to higher costs for the base station buyers. These higher costs as well as the costs for the real estate necessary to house the base station have motivated the development of several base station standardization initiatives. For example, a cellular telephony consortium developed a standardized interface denoted as the Common Public Radio Interface (CPRI). A competing standard known as the Open Base Station Architecture Initiative (OBSAI) has also been developed. In a CPRI system, the base stations, which comprise part of what is referred to as Radio Equipment Control, are located remotely from the cellular amplifiers and antennas—the amplifiers and antennas being part of what is denoted as Radio Equipment. A similar separation between a radio head and a base station server exists in the OBSAI protocol such that both CPRI and OBSAI enabled a distributed architecture. In this fashion, a CPRI or OBSAI base station need not be located in a costly (and environmentally challenging) location such as urban rooftops or adjacent power station towers that hold the radio head. In addition, the standardized nature of these protocols offers inherent cost savings to cellular providers as equipment providers must directly compete with each other because they offer the same standardized equipment. As a result, cellular telephony systems organized according to the CPRI or OBSAI protocol are growing in popularity.
This popularity has introduced some complexity in that radio base station systems have very strict link timing accuracy requirements with regard to data path latency between components. But such strict timing accuracy is necessary so the varying equipment vendors who incorporate standardized interfaces such as CPRI into their designs can produce equipment that can be integrated into a resulting system that meets overall system-level latency requirements. To meet such stringent latency requirements, it is common to accurately control the latency variation that exists in the elements implementing the data path. By accurately controlling the latency variation, the overall latency through the link components can be essentially fixed for a given design. But such accurate control is problematic when the digital logic implementing the interface contains elements that have inherently-high latency variation. For example, the use of First-In-First-Out (FIFO) buffers to transfer data between different clock domains introduces a variable amount of buffer delay in the data path. In addition, it is often desirable to use a properly-configured programmable logic device such as a Field Programmable Gate Array (FPGA) to implement a CPRI interface. But the resulting FPGA logic will vary from design to design and thus introduce variable amounts of delay accordingly.
To control the delay variation in the FPGA logic, it is common to bypass any FIFOs in the FPGA's Physical Coding Sublayer (PCS) SErializer-DESerializer (SERDES) modules. Such modules are necessary since the data in the standardized interface such as CPRI arrives in high speed serialized form that must be parallelized by the SERDES so that the lower speed clock in an FPGA can accommodate the necessary data processing. Typically, the logic in such modules is hardwired as opposed to the programmable logic in the FPGA core. Not only are these FIFOs avoided but it is also common to avoid the use of any FIFOs in the FPGA core to control the delay variation. Thus, the resulting FPGA design must tightly control all data transfers between different clock domains by constraining the phase difference between the clocks. Despite such precautions, it is still necessary to measure the latency from one FPGA route to the next using labor-intensive software tools. As a result, the design of standardized interfaces such as CPRI interfaces in FPGA logic is highly constrained and difficult.
Accordingly, there is a need in the art for improved techniques for measuring the latency of data paths within an FPGA.